1. Field of the Invention
The present invention generally relates to a layout configuration for a memory cell array, and more particularly, to a layout configuration for a static random access memory (hereinafter abbreviated as SRAM) array.
2. Description of the Prior Art
In recent years, with widespread used of mobile terminal equipment, digital signal processing in which bulk data such as sounds or images is processed at high speed has been increasingly important. SRAM, which is capable of high-speed access processing holds an important place as a semiconductor memory device to be mounted on such mobile terminal equipment.
Please refer to FIG. 1, which is a plan view of a conventional memory cell layout configuration of a 6T-SRAM. The memory cell 100 includes four n-channel metal-oxide-semiconductor (MOS) transistors 106/108/110/112 formed in heavily-doped p-type (P+) regions 120 and two p-channel MOS transistors 102/104 formed in a heavily-doped n-type (N+) region 122.
Please refer to FIG. 2, which is a plan view of a conventional memory cell array layout configuration of the SRAM. As shown in FIG. 2, each memory cell 100, which is indicated as an area enclosed by a dotted line is formed on the P+ regions 120 and the N+ region 122 between the two adjacent P+ regions 120. It should be noted that the P+ regions 120 and the N+ regions 122 are all indicated as areas enclosed by thin solid lines. Furthermore, a row of strapping cells (not shown) are positioned between two rows of the memory cells 100 for power feeding. The strapping cells include a plurality of P+ regions 130 and a plurality of N+ regions 132, which are indicated as areas enclosed by thick solid lines. The P+ regions 130 are formed simultaneously with the P+ regions 120 and the N+ regions 132 are formed simultaneously with the N+ regions 122. As shown in FIG. 2, the P+ regions 130 and the N+ regions 122 in a same column are alternately arranged. In the same concept, the N+ regions 132 and the P+ regions 120 in a same column are alternately arranged. Furthermore, the P+ regions 130 and the N+ regions 132 in the same row are alternately arranged.
Additionally, a plurality of diffusion regions (not shown) respectively serving as the source/drain regions of the n-channel MOS transistors and the p-channel MOS transistors are formed in the P+ regions 120 and the N+ regions 122. Also a plurality of diffusion regions 140 is respectively formed in the P+ regions 130 and the N+ regions 132. As shown in FIG. 2, the diffusion regions 140 is completely encompassed by the P+ regions 130 and the N+ regions 132.
It is noteworthy that with a trend toward higher integration of integrated circuit, semiconductor devices such as the memory cells 100 keep shrinking. However, it is found that the memory cell array 200 cannot be shrunk as expected. It is noteworthy that in the prior art memory cell array 200, the P+ regions 120, the N+ regions 122, the P+ regions 130, and the N+ regions 132 are all islanding configurations. Furthermore, the P+ region 130 must be kept from the corner of the P+ regions 120 by a spacing distance d1 which satisfies with the topological layout rules (TLR), and the N+ region 132 must be kept from the corner of the N+ regions 122 by a spacing distance d2 which satisfies with the TLR. In other words, the spacing distances d1 and d2 cannot be reduced in order to be compliant with the fabricator's TLR, and thus the size of the memory cell array 200 cannot be shrunk. Not only the spacing distances d1 and d2 cannot be reduced, but also the size of the P+ regions 130 and the N+ regions 132 cannot be shrunk due to optical limitations. Furthermore, it is found that the layout configuration of the conventional memory cell array 200 has many TLR design rule check (DRC) violation and causes many risks such as incomplete opening in masking layer for forming the P+ regions 130, the N+ regions 132, and even the diffusion regions 140, and causes inferior implantation result. As such, a layout configuration allowing memory cell array shrinking is still in need.